1. Field of the Invention
The present invention relates to a semiconductor device including a memory cell region, a peripheral circuit region and transistors provided in the respective regions, and a method of fabricating the same.
2. Description of the Related Art
A fabricating process of semiconductor devices generally includes a number of times of a photolithography process. Since multi-functionalization and refinement of semiconductor devices have been progressing year by year, a reduction in the fabricating process for reducing the fabrication cost has merits in connection with both an improvement in the yield and cost reduction.
However, reducing the number of times of the photolithography process means reducing the number of photomasks to be produced. Actually, the number of processes using photomasks cannot be reduced simply in relation with other processes. For example, JP-A-2003-7817 discloses a technique for simultaneously forming a bit line contact hole, a contact hole to a peripheral circuit and a gate contact hole. Etching is performed to form each contact hole simultaneously with the sidewall of a plurality of gate structures as an etching mask under the condition of larger etching selection ratio of oxide to nitride and continuously under the condition of larger etching selection ratio of nitride to oxide and larger etching rate of nitride in a perpendicular direction than that in a lateral direction. Consequently, the aforesaid effect can be achieved since the number of times of the photolithography process is reduced as compared with the process in which the contact holes are formed separately.
However, the foregoing reference is directed to integration of photolithography processes concerning forming contact holes. It is conceivable that another problem will occur when the photolithography process is integrated with another kind of process. Thus, the integration cannot easily be carried out. Accordingly, there is a case where it is difficult to integrate the photolithography processes since processing contents differ from each other in spite of similarity in mask patterns. For example, patterns of photomasks are similar to each other between a process in which a threshold is adjusted by implanting ions into a lower part of the gate electrode in order that a cutoff characteristic of a select gate transistor to be formed in a memory cell region may be improved and another process in which an oxide film formed after gate formation is peeled. However, it is difficult to integrate these processes because of slight difference in the patterns. More specifically, a mask used to form a resist pattern for ion implantation is open only between select gates in the memory cell regions. On the other hand, the mask pattern used to peel the oxide film is designed to be open in a part corresponding to a contact of a peripheral circuit region since the pattern is used to peel an oxide film on a part corresponding to the contact so as to correspond to a process of forming an opening of a contact window.
Accordingly, when the ion implantation is to be carried out with the mask pattern used in the process of peeling the oxide film, impurity is doped into the contact region of the peripheral circuit region. Since a transistor with high breakdown voltage is formed, there is a possibility that necessary breakdown voltage cannot be obtained because of high impurity density.
Furthermore, when the mask pattern for the ion implantation is used in the process of peeling an oxide film, the oxide film cannot be peeled in the transistor of the peripheral circuit. As a result, a malfunction may result from difference between film thicknesses of films.